[RISCV][GISel] Add manual instruction selection for i8/i16/i32->i32/i64 G_SEXT/G_ZEXT. (#161971)HEADmain

Because GISel doesn't distinquish integer and FP types, we need to allow
s16/s32 as legal inputs/outputs of G_SEXT and G_ZEXT.

This requires a extra isel patterns to support the cross product of
these types that we don't need for SelectionDAG. We also needed to add
i16/i32 to the GPR register class which prevents some type inferencing
in tablegen and increases the size of the RISCVGenDAGISel.inc by 2K.

This patch proposes to do manual selection so we can remove these
patterns and eventually remove the types from the register class.

0 files changed, 0 insertions, 0 deletions