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authorSimon Pilgrim <llvm-dev@redking.me.uk>2025-10-14 16:20:17 +0100
committerGitHub <noreply@github.com>2025-10-14 15:20:17 +0000
commitf4359301c033694d36865c7560714164d2050240 (patch)
tree215f0325d20fbc4b05b65483eefc7104cdf7d2ab /mlir/lib/Dialect/Linalg/IR
parentb2797d9b8236a40ee30d6daf4e603a82da9a94d4 (diff)
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[X86] combineVectorSizedSetCCEquality - allow 256/512-bit vector icmp_ne/eq zero comparisons (#163373)HEADmain
We avoid creating vector movmsk/ptest comparisons with zero if we can just use scalar OR instead, but this doesn't make sense for 256-bit or larger vectors which creates a more complex OR chain. This more closely matches what we do for icmp_ne/eq against non-zero values. I'm hoping that we can eventually allow even larger vectors to be handled with a OR/AND chains - but for now this just allows us to handle legal 256/512-bit vector widths.
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