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| author | Lukacma <Marian.Lukac@arm.com> | 2024-07-02 11:37:52 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-02 11:37:52 +0200 |
| commit | 9ceb45cc191628926496bd33b4d52011ed519151 (patch) | |
| tree | 643b0552b541521a09c097a20d7f65620b33ce77 /mlir/lib/Bytecode/Reader/BytecodeReader.cpp | |
| parent | d7da0ae4f46cb8731910cc30251105c88aeae12c (diff) | |
| download | llvm-9ceb45cc191628926496bd33b4d52011ed519151.zip llvm-9ceb45cc191628926496bd33b4d52011ed519151.tar.gz llvm-9ceb45cc191628926496bd33b4d52011ed519151.tar.bz2 | |
[AArch64][SVE] optimisation for unary SVE store intrinsics with no active lanes (#95793)
This patch extends https://github.com/llvm/llvm-project/pull/73964 and
adds optimisation of store SVE intrinsics when predicate is zero.
Diffstat (limited to 'mlir/lib/Bytecode/Reader/BytecodeReader.cpp')
0 files changed, 0 insertions, 0 deletions