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| author | David Green <david.green@arm.com> | 2023-09-17 09:50:12 +0100 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2023-09-17 09:50:12 +0100 |
| commit | 2861ec84fce21c2ec9f33849e38661b9f4fe62e2 (patch) | |
| tree | ea4cf4226430c1dd0a98058f292d6d5473853989 /mlir/lib/Bytecode/Reader/BytecodeReader.cpp | |
| parent | 9f7906a6c075b3881a3b4e6bd2236c26c774e0da (diff) | |
| download | llvm-2861ec84fce21c2ec9f33849e38661b9f4fe62e2.zip llvm-2861ec84fce21c2ec9f33849e38661b9f4fe62e2.tar.gz llvm-2861ec84fce21c2ec9f33849e38661b9f4fe62e2.tar.bz2 | |
[AArch64][GlobalISel] Add lowering for constant BIT/BIF/BSP (#65897)
The non-constant bit/bif/bsp already work through tablegen patterns, this
patch handles the constant case, mirroring the basic support for
`or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded
to either BIT, BIF or BSL depending on the best register allocation.
G_BIT can be replaced with G_BSP as a more general alternative.
Diffstat (limited to 'mlir/lib/Bytecode/Reader/BytecodeReader.cpp')
0 files changed, 0 insertions, 0 deletions