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author | Farzon Lotfi <farzonlotfi@microsoft.com> | 2025-08-12 17:43:30 -0400 |
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committer | GitHub <noreply@github.com> | 2025-08-12 17:43:30 -0400 |
commit | 1ca8ad29dbbe4255cb19fb1193a88040dda515a9 (patch) | |
tree | c8073ffba4f479a4b7e0d3de21e1d018461aee33 /mlir/lib/Bindings/Python/IRModule.h | |
parent | 116c318225b1d6b198baf22312a6bd980b80b135 (diff) | |
download | llvm-1ca8ad29dbbe4255cb19fb1193a88040dda515a9.zip llvm-1ca8ad29dbbe4255cb19fb1193a88040dda515a9.tar.gz llvm-1ca8ad29dbbe4255cb19fb1193a88040dda515a9.tar.bz2 |
[SPIRV] Create a new OpSelect selector and fix register types. (#152311)
fixes #135572
There are two problems that are causing problems first register types
are copied from older registers instead of evaluating the spirv types.
Second the way OpSelect is defined in SPIRVInstrInfo.td we always
default to integer for TernOpTyped. There seems to be a problem of
multiple matches in the getMatchTable so when executeMatchTable runs we
aren't getting the right opSelect.
Correcting the tablegen wasn't very easy so instead created an emitter
for Select that evaluated the register types. this passes the original
llvm/test/CodeGen/SPIRV/instructions/select.ll tests and the new float
ones I'm adding in issue-135572-emit-float-opselect.ll
Diffstat (limited to 'mlir/lib/Bindings/Python/IRModule.h')
0 files changed, 0 insertions, 0 deletions