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| author | Rajat Bajpai <rbajpai@nvidia.com> | 2025-10-13 19:26:32 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-13 19:26:32 +0530 |
| commit | 885da07a9fb169f45ba19c2ff20c7b7fccaa27c5 (patch) | |
| tree | f0d0d0814a4f8abbfcf46d7303835231cfa54abd /mlir/lib/Bindings/Python/DialectTransform.cpp | |
| parent | 0dd51f92fc2390f7fc7fb527b156de1bd8478afd (diff) | |
| download | llvm-885da07a9fb169f45ba19c2ff20c7b7fccaa27c5.zip llvm-885da07a9fb169f45ba19c2ff20c7b7fccaa27c5.tar.gz llvm-885da07a9fb169f45ba19c2ff20c7b7fccaa27c5.tar.bz2 | |
[NVPTX] Update architecture support checks for tcgen05 intrinsics (#161519)
This change updates architecture support checks for tcgen05 intrinsics
(except tcgen05.mma.*). The newer checks will support family-specific
architecture variants as well. After this change, the arch checks will
be accurate and match with PTX ISA.
Intrinsics affected:
- tcgen05.ld/st
- tcgen05.alloc/dealloc/relinquish
- tcgen05.cp
- tcgen05.fence/wait
- tcgen05.commit
- tcgen05.shift
Diffstat (limited to 'mlir/lib/Bindings/Python/DialectTransform.cpp')
0 files changed, 0 insertions, 0 deletions