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author | Craig Topper <craig.topper@intel.com> | 2018-05-10 00:05:13 +0000 |
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committer | Craig Topper <craig.topper@intel.com> | 2018-05-10 00:05:13 +0000 |
commit | 2b248849aecbfd726348f320e80e12a3b91c9f48 (patch) | |
tree | 24a002de727174e27309a8ef81f71e94d456bde2 /llvm/utils/lit/tests/test-output.py | |
parent | 069a1eb3bbcb9d959ae8d61738c8b98a5398096a (diff) | |
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[Builtins] Improve the IR emitted for MSVC compatible rotr/rotl builtins to match what the middle and backends understand
Previously we emitted something like
rotl(x, n) {
n &= bitwidth-1;
return n != 0 ? ((x << n) | (x >> (bitwidth - n)) : x;
}
We use a select to avoid the undefined behavior on the (bitwidth - n) shift.
The middle and backend don't really recognize this as a rotate and end up emitting a cmov or control flow because of the select.
A better pattern is (x << (n & mask)) | (x << (-n & mask)) where mask is bitwidth - 1.
Fixes the main complaint in PR37387. There's still some work to be done if the user writes that sequence directly on a short or char where type promotion rules can prevent it from being recognized. The builtin is emitting direct IR with unpromoted types so that isn't a problem for it.
Differential Revision: https://reviews.llvm.org/D46656
llvm-svn: 331943
Diffstat (limited to 'llvm/utils/lit/tests/test-output.py')
0 files changed, 0 insertions, 0 deletions