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| author | Alexandros Lamprineas <alexandros.lamprineas@arm.com> | 2022-07-18 08:07:59 +0100 |
|---|---|---|
| committer | Alexandros Lamprineas <alexandros.lamprineas@arm.com> | 2022-07-20 09:47:32 +0100 |
| commit | 051738b08cf5e39fd274dd379147d1c19e2b5b20 (patch) | |
| tree | 472fec031051640a2ca7691b809d7806d9bfa392 /llvm/utils/UpdateTestChecks/asm.py | |
| parent | ee7ccbeaa7d388dc9f7844f3d63ac07c3430d2ab (diff) | |
| download | llvm-051738b08cf5e39fd274dd379147d1c19e2b5b20.zip llvm-051738b08cf5e39fd274dd379147d1c19e2b5b20.tar.gz llvm-051738b08cf5e39fd274dd379147d1c19e2b5b20.tar.bz2 | |
Reland "[AArch64] Add a tablegen pattern for UZP2."
Converts concat_vectors((trunc (lshr)), (trunc (lshr))) to UZP2
when the shift amount is half the width of the vector element.
Prioritize the ADDHN(2), SUBHN(2) patterns over UZP2.
Fixes https://github.com/llvm/llvm-project/issues/52919
Differential Revision: https://reviews.llvm.org/D130061
Diffstat (limited to 'llvm/utils/UpdateTestChecks/asm.py')
0 files changed, 0 insertions, 0 deletions