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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2014-11-23 08:07:43 +0000 |
|---|---|---|
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2014-11-23 08:07:43 +0000 |
| commit | 9e5089a9384c146c0d277b4962c2345e92ff4a88 (patch) | |
| tree | 3a01ebfa31ad635c396e816fedc8dce9f24d38e0 /llvm/utils/TableGen/CodeGenTarget.cpp | |
| parent | 2a495975ed265fd249044afb83e4416df68410b9 (diff) | |
| download | llvm-9e5089a9384c146c0d277b4962c2345e92ff4a88.zip llvm-9e5089a9384c146c0d277b4962c2345e92ff4a88.tar.gz llvm-9e5089a9384c146c0d277b4962c2345e92ff4a88.tar.bz2 | |
Masked Vector Load and Store Intrinsics.
Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores.
Added SDNodes for masked operations and lowering patterns for X86 code generator.
Examples:
<16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask)
declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask)
Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch.
http://reviews.llvm.org/D6191
llvm-svn: 222632
Diffstat (limited to 'llvm/utils/TableGen/CodeGenTarget.cpp')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenTarget.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp index 597da68..f4f5e2b 100644 --- a/llvm/utils/TableGen/CodeGenTarget.cpp +++ b/llvm/utils/TableGen/CodeGenTarget.cpp @@ -539,7 +539,8 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { // variants with iAny types; otherwise, if the intrinsic is not // overloaded, all the types can be specified directly. assert(((!TyEl->isSubClassOf("LLVMExtendedType") && - !TyEl->isSubClassOf("LLVMTruncatedType")) || + !TyEl->isSubClassOf("LLVMTruncatedType") && + !TyEl->isSubClassOf("LLVMVectorSameWidth")) || VT == MVT::iAny || VT == MVT::vAny) && "Expected iAny or vAny type"); } else |