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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-24 07:16:37 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-24 07:16:37 +0000 |
| commit | c8e2ce4046d021e37a0910867731e7127bc59422 (patch) | |
| tree | ddfda102a8bbe2a1d05d6ffd8b580368fab0c3e8 /llvm/utils/TableGen/CodeGenMapTable.cpp | |
| parent | 68acf7acd28fc09fce13c956461337e9a7e3a1ac (diff) | |
| download | llvm-c8e2ce4046d021e37a0910867731e7127bc59422.zip llvm-c8e2ce4046d021e37a0910867731e7127bc59422.tar.gz llvm-c8e2ce4046d021e37a0910867731e7127bc59422.tar.bz2 | |
AMDGPU: Reduce number of copies emitted
Instead of always inserting a copy in case
the super register is itself a subregister,
only extract to the super reg class if this is
actually the case.
This shouldn't really change codegen, but
makes looking at the output of SIFixSGPRCopies
easier to read.
llvm-svn: 248467
Diffstat (limited to 'llvm/utils/TableGen/CodeGenMapTable.cpp')
0 files changed, 0 insertions, 0 deletions