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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-15 20:20:18 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-15 20:20:18 +0000 |
| commit | 66ee934440c21dc2bd6ff938c79dad4ce032990a (patch) | |
| tree | 9e1b6a705bf48bea2474c236a13667141026056b /llvm/utils/TableGen/CodeGenDAGPatterns.cpp | |
| parent | dfcd4384cbcac0eeb7e5cbce350f875ba4da79d5 (diff) | |
| download | llvm-66ee934440c21dc2bd6ff938c79dad4ce032990a.zip llvm-66ee934440c21dc2bd6ff938c79dad4ce032990a.tar.gz llvm-66ee934440c21dc2bd6ff938c79dad4ce032990a.tar.bz2 | |
AMDGPU/GlobalISel: Allow scalar s1 and/or/xor
If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to
whether the result is 0. If the inputs are SCC, these can be copied to
a 32-bit SGPR to produce an SCC result.
llvm-svn: 366125
Diffstat (limited to 'llvm/utils/TableGen/CodeGenDAGPatterns.cpp')
0 files changed, 0 insertions, 0 deletions