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| author | Jonathan Thackray <jonathan.thackray@arm.com> | 2025-10-23 23:31:33 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-23 23:31:33 +0100 |
| commit | 66e8270e8f3cd5a291e48097095c4f547ddf417d (patch) | |
| tree | 6d2a6d4b64a909bd8fd7554678387e96d8f18ff0 /llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp | |
| parent | f28224b78f9ef8c0017a62b9db19338fbd051394 (diff) | |
| download | llvm-66e8270e8f3cd5a291e48097095c4f547ddf417d.zip llvm-66e8270e8f3cd5a291e48097095c4f547ddf417d.tar.gz llvm-66e8270e8f3cd5a291e48097095c4f547ddf417d.tar.bz2 | |
[AArch64][llvm] Armv9.7-A: Add support for TLBI Domains (FEAT_TLBID) (#163156)
Allow the following `TLBI` operation types to take an optional register
operand when enabled by `FEAT_TLBID`:
- ALL*
- VMALL*
- VMALLS12*
- VMALLWS2*
as documented here:
* https://developer.arm.com/documentation/ddi0602/2025-09/
* https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
Notes on implementation:
Currently, AArch64 `SYS` alias instructions fall into two categories:
* a register value must be present (indicated by any value except `XZR`)
* no register value must be present (this value must be `XZR`)
When +tblid is enabled, `SYS` aliases are now allowed to take an optional
register, or no register as before. We need an extra tablegen flag to
indicate if the register is optional or not (the existing "NeedsReg" flag
is binary and not suitable; the register is either present or absent,
not either for a specific TLBI operation)
Don't produce an error message if the register operand is missing or
unexpected, if it is specified as an optional register.
Diffstat (limited to 'llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp')
0 files changed, 0 insertions, 0 deletions