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| author | luxufan <luxufan@iscas.ac.cn> | 2022-10-19 14:34:05 +0800 |
|---|---|---|
| committer | luxufan <luxufan@iscas.ac.cn> | 2022-10-19 16:15:14 +0800 |
| commit | 82c820b95cf7ec284baf182cf838ca9e26758098 (patch) | |
| tree | 401db55dd45b3d958d14b38d2b41609b5d01cf74 /llvm/unittests/Support/TargetParserTest.cpp | |
| parent | 2ca5fcb424e863ec34c839377515b3c684bbed00 (diff) | |
| download | llvm-82c820b95cf7ec284baf182cf838ca9e26758098.zip llvm-82c820b95cf7ec284baf182cf838ca9e26758098.tar.gz llvm-82c820b95cf7ec284baf182cf838ca9e26758098.tar.bz2 | |
[RISCV] Enable the LocalStackSlotAllocation pass support
For RISC-V, load/store(exclude vector load/store) instructions only
has a 12 bit immediate operand. If the offset is out-of-range, it
must make use of a temp register to make up this offset. If between
these offsets, they have a small(IsInt<12>) relative offset,
LocalStackSlotAllocation pass can find a value as frame base register's
value, and replace the origin offset with this register's value plus
the relative offset.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D98101
Diffstat (limited to 'llvm/unittests/Support/TargetParserTest.cpp')
0 files changed, 0 insertions, 0 deletions