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| author | Rahul Anand R <rahul@rrlogic.co.in> | 2022-05-09 10:28:20 +0100 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2022-05-09 10:28:20 +0100 |
| commit | 7dcd0ea683ed3175bc3ec6aed24901a9d504182e (patch) | |
| tree | 848dd949754e4cce1f1cec82217bce5707417f28 /llvm/unittests/Support/TargetParserTest.cpp | |
| parent | fa593b079b76f1c30d684cfe42a662fed157e2e5 (diff) | |
| download | llvm-7dcd0ea683ed3175bc3ec6aed24901a9d504182e.zip llvm-7dcd0ea683ed3175bc3ec6aed24901a9d504182e.tar.gz llvm-7dcd0ea683ed3175bc3ec6aed24901a9d504182e.tar.bz2 | |
[AArch64] Generate AND in place of CSEL for predicated CTTZ
This patch implements a for a target specific optimization that replaces
the cmp and csel from cttz with an and mask.
Differential Revision: https://reviews.llvm.org/D123782
Diffstat (limited to 'llvm/unittests/Support/TargetParserTest.cpp')
0 files changed, 0 insertions, 0 deletions