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| author | Gadi Haber <gadi.haber@intel.com> | 2017-08-28 10:04:16 +0000 |
|---|---|---|
| committer | Gadi Haber <gadi.haber@intel.com> | 2017-08-28 10:04:16 +0000 |
| commit | d76f7b824e57b40fb87d8401d36af5b54d304542 (patch) | |
| tree | 547e4ab05720649f25f1613cbfb6d0c302c5c3fd /llvm/unittests/Support/CommandLineTest.cpp | |
| parent | 60608a8ae55041cc47f0458570af897bda8a3123 (diff) | |
| download | llvm-d76f7b824e57b40fb87d8401d36af5b54d304542.zip llvm-d76f7b824e57b40fb87d8401d36af5b54d304542.tar.gz llvm-d76f7b824e57b40fb87d8401d36af5b54d304542.tar.bz2 | |
[X86][Haswell] Updating HSW instruction scheduling information
This patch completely replaces the instruction scheduling information for the Haswell architecture target by modifying the file X86SchedHaswell.td located under the X86 Target.
We used the scheduling information retrieved from the Haswell architects in order to replace and modify the existing scheduling.
The patch continues the scheduling replacement effort started with the SNB target in r307529 and r310792.
Information includes latency, number of micro-Ops and used ports by each HSW instruction.
Please expect some performance fluctuations due to code alignment effects.
Reviewers: RKSimon, zvi, aymanmus, craig.topper, m_zuckerman, igorb, dim, chandlerc, aaboud
Differential Revision: https://reviews.llvm.org/D36663
llvm-svn: 311879
Diffstat (limited to 'llvm/unittests/Support/CommandLineTest.cpp')
0 files changed, 0 insertions, 0 deletions