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| author | Aaditya <115080342+easyonaadit@users.noreply.github.com> | 2025-10-03 13:38:37 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-03 13:38:37 +0530 |
| commit | 19cd5bd350b730da35629de5095764861f70ecee (patch) | |
| tree | ff996a776c9e1afedfc53aa1045ebcb5eaea3a0a /llvm/unittests/Object/BuildIDTest.cpp | |
| parent | a1db40fef857cc11a38fdec1395b2731e73ca085 (diff) | |
| download | llvm-19cd5bd350b730da35629de5095764861f70ecee.zip llvm-19cd5bd350b730da35629de5095764861f70ecee.tar.gz llvm-19cd5bd350b730da35629de5095764861f70ecee.tar.bz2 | |
[AMDGPU] Account for implicit XCNT insertion (#160812)
Hardware inserts an implicit `S_WAIT_XCNT 0` between
alternate SMEM and VMEM instructions, so there are
never outstanding address translations for both SMEM
and VMEM at the same time.
Diffstat (limited to 'llvm/unittests/Object/BuildIDTest.cpp')
0 files changed, 0 insertions, 0 deletions