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| author | Ties Stuij <ties.stuij@arm.com> | 2022-11-22 12:38:47 +0000 |
|---|---|---|
| committer | Ties Stuij <ties@stuij.se> | 2022-11-22 14:23:12 +0000 |
| commit | cb261e30fbb174085d2eea4f4afc3cef2838b7f7 (patch) | |
| tree | 32b759acfadd45f00f6958e04691f56110f23ec5 /llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp | |
| parent | 9e7febb4f73c8584f622d4dad17be5417938eb10 (diff) | |
| download | llvm-cb261e30fbb174085d2eea4f4afc3cef2838b7f7.zip llvm-cb261e30fbb174085d2eea4f4afc3cef2838b7f7.tar.gz llvm-cb261e30fbb174085d2eea4f4afc3cef2838b7f7.tar.bz2 | |
[AArch64][clang] implement 2022 General Data-Processing instructions
This patch implements the 2022 Architecture General Data-Processing Instructions
They include:
Common Short Sequence Compression (CSSC) instructions
- scalar comparison instructions
SMAX, SMIN, UMAX, UMIN (32/64 bits) with or without immediate
- ABS (absolute), CNT (count non-zero bits), CTZ (count trailing zeroes)
- command-line options for CSSC
Associated with these instructions in the documentation is the Range Prefetch
Memory (RPRFM) instruction, which signals to the memory system that data memory
accesses from a specified range of addresses are likely to occur in the near
future. The instruction lies in hint space, and is made unconditional.
Specs for the individual instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/
contributors to this patch:
- Cullen Rhodes
- Son Tuan Vu
- Mark Murray
- Tomas Matheson
- Sam Elliott
- Ties Stuij
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D138488
Diffstat (limited to 'llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp')
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