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| author | Kevin Qin <Kevin.Qin@arm.com> | 2014-01-13 01:56:29 +0000 |
|---|---|---|
| committer | Kevin Qin <Kevin.Qin@arm.com> | 2014-01-13 01:56:29 +0000 |
| commit | 21e8f1c4eb62e1af96c4768ad77614d0b320bf21 (patch) | |
| tree | 4fa52dc6e75e7aacfbfab180587d10fcc29b0f8e /llvm/unittests/Bitcode/BitReaderTest.cpp | |
| parent | a6505ca4c2225828277fc9fba85dab5e477bd6d1 (diff) | |
| download | llvm-21e8f1c4eb62e1af96c4768ad77614d0b320bf21.zip llvm-21e8f1c4eb62e1af96c4768ad77614d0b320bf21.tar.gz llvm-21e8f1c4eb62e1af96c4768ad77614d0b320bf21.tar.bz2 | |
[AArch64 NEON] Add more scenarios to use perm instructions when lowering shuffle_vector
This patch covered 2 more scenarios:
1. Two operands of shuffle_vector are the same, like
%shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
2. One of operands is undef, like
%shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
After this patch, perm instructions will have chance to be emitted instead of lots of INS.
llvm-svn: 199069
Diffstat (limited to 'llvm/unittests/Bitcode/BitReaderTest.cpp')
0 files changed, 0 insertions, 0 deletions