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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-10-03 21:19:48 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-03 21:19:48 +0900 |
| commit | e3d23f85737863c1ffc7b757b729df1903ca30b7 (patch) | |
| tree | 8a5645c4633a1eb9d95027a613a28d9b96e1dc98 /llvm/unittests/Analysis/FunctionPropertiesAnalysisTest.cpp | |
| parent | 5601c4080abfdd362415cb0406de64c685edca67 (diff) | |
| download | llvm-e3d23f85737863c1ffc7b757b729df1903ca30b7.zip llvm-e3d23f85737863c1ffc7b757b729df1903ca30b7.tar.gz llvm-e3d23f85737863c1ffc7b757b729df1903ca30b7.tar.bz2 | |
AMDGPU: Fix trying to constrain physical registers in spill handling (#161793)
It's nonsensical to call constrainRegClass on a physical register,
and we should not see virtual registers here.
Diffstat (limited to 'llvm/unittests/Analysis/FunctionPropertiesAnalysisTest.cpp')
0 files changed, 0 insertions, 0 deletions