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| author | David Green <david.green@arm.com> | 2023-01-17 15:49:29 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2023-01-17 15:49:29 +0000 |
| commit | 1f2c37afbe69d048bc518363454ae073f588066e (patch) | |
| tree | 2c994c25ce0a33ccaa70ab203a28d19800ec300c /llvm/unittests/ADT/ArrayRefTest.cpp | |
| parent | 004e613ce41fc14327e9b4bf215378a6150fe812 (diff) | |
| download | llvm-1f2c37afbe69d048bc518363454ae073f588066e.zip llvm-1f2c37afbe69d048bc518363454ae073f588066e.tar.gz llvm-1f2c37afbe69d048bc518363454ae073f588066e.tar.bz2 | |
[AArch64][SVE] Implement isVScaleKnownToBeAPowerOfTwo
According to https://developer.arm.com/documentation/102105/ia-00/?lang=en
> Arm is making a retrospective change to the SVE architecture to remove
> the capability of selecting a non-power-of-two vector length in
> non-Streaming SVE as well as in Streaming SVE mode. Specific updates as
> a result of this change will be communicated in due course.
This patch implements the isVScaleKnownToBeAPowerOfTwo method to teach
DAG Combines that VScale will be known to be a power of 2, which helps
reduce or simplify some expressions (notably the udiv in vector trip
count expressions).
Differential Revision: https://reviews.llvm.org/D141486
Diffstat (limited to 'llvm/unittests/ADT/ArrayRefTest.cpp')
0 files changed, 0 insertions, 0 deletions