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| author | Srividya Karumuri <srividya_karumuri@apple.com> | 2021-11-29 16:25:21 -0800 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2021-11-30 13:54:52 -0800 |
| commit | 9e3e1aad3161f4ce5301c3a59c7313ad83240a6d (patch) | |
| tree | 7690e36b144da41839fac86a38d9e40be2911c42 /llvm/unittests/ADT/APIntTest.cpp | |
| parent | 7e6df41f655e51c984b92bbd9c19a6fb851f35d4 (diff) | |
| download | llvm-9e3e1aad3161f4ce5301c3a59c7313ad83240a6d.zip llvm-9e3e1aad3161f4ce5301c3a59c7313ad83240a6d.tar.gz llvm-9e3e1aad3161f4ce5301c3a59c7313ad83240a6d.tar.bz2 | |
[InstCombine] Allow fake vector insert folding to bit-logic only if the insert element is integer type
The below commit is causing assertion when insert element type is not integer
type such as half. This is because the transformation is creating zext before
doing bitwise OR, and the zext is supported only for integer types
https://github.com/llvm/llvm-project/commit/80ab06c599a0f5a90951c36a57b2a9b492b19d61
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D114734
Diffstat (limited to 'llvm/unittests/ADT/APIntTest.cpp')
0 files changed, 0 insertions, 0 deletions