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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-02-20 12:42:54 +0000 |
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| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-02-20 12:42:54 +0000 |
| commit | 0ccdd1315b74e9a5aaf1b967dd2d7967e24211b8 (patch) | |
| tree | 6063cb7bb3d0fe341764661640098b9555d964f8 /llvm/unittests/ADT/APIntTest.cpp | |
| parent | ac05bc0556f764791b07d87d1812759a856f4720 (diff) | |
| download | llvm-0ccdd1315b74e9a5aaf1b967dd2d7967e24211b8.zip llvm-0ccdd1315b74e9a5aaf1b967dd2d7967e24211b8.tar.gz llvm-0ccdd1315b74e9a5aaf1b967dd2d7967e24211b8.tar.bz2 | |
I optimized the following patterns:
sext <4 x i1> to <4 x i64>
sext <4 x i8> to <4 x i64>
sext <4 x i16> to <4 x i64>
I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.
I also added a cost of this operations to the AVX costs table.
llvm-svn: 175619
Diffstat (limited to 'llvm/unittests/ADT/APIntTest.cpp')
0 files changed, 0 insertions, 0 deletions