llvm-reduce: Add reduction pass to remove regalloc hints

I'm a bit confused by what's actually stored for the allocation
hints. The MIR parser only handles the "simple" case where there's a
single hint. I don't really understand the assertion in
clearSimpleHint, or under what circumstances there are multiple hint
registers.

1 files changed, 6 insertions, 0 deletions

diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
index 91ea752..fbae2a6 100644
--- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -496,6 +496,12 @@ static uint64_t computeMIRComplexityScoreImpl(const MachineFunction &MF) {
   // Add in the block count.
   Score += 2 * MF.size();
 
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+    Register Reg = Register::index2VirtReg(I);
+    Score += MRI.getRegAllocationHints(Reg).second.size();
+  }
+
   for (const MachineBasicBlock &MBB : MF) {
     for (const MachineInstr &MI : MBB) {
       const unsigned Opc = MI.getOpcode();