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| author | Dmitrii Petrov <dmitrii.petrov@syntacore.com> | 2022-12-14 11:12:23 +0300 |
|---|---|---|
| committer | Anton Afanasyev <anton.afanasyev@syntacore.com> | 2022-12-14 11:45:44 +0300 |
| commit | c86a878e8995d54a5b950098e81f0d3bf153aded (patch) | |
| tree | 5e8e0ede70ad426ba7cb3c34ce66c4c3b3a8e36f /llvm/tools/llvm-readobj/llvm-readobj.cpp | |
| parent | 8a55264be311bf54ddef0430c712ad51a80a5f7f (diff) | |
| download | llvm-c86a878e8995d54a5b950098e81f0d3bf153aded.zip llvm-c86a878e8995d54a5b950098e81f0d3bf153aded.tar.gz llvm-c86a878e8995d54a5b950098e81f0d3bf153aded.tar.bz2 | |
[RISCV] Add Syntacore SCR1 CPU model
SCR1 is available at https://github.com/syntacore/scr1
'syntacore-scr1-base' corresponds to SCR1_CFG_RV32IC_BASE,
'syntacore-scr1-max' corresponds to SCR1_CFG_RV32IMC_MAX.
SCR1_CFG_RV32EC_MIN is RV32EC, which is currently unsupported.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D139302
Diffstat (limited to 'llvm/tools/llvm-readobj/llvm-readobj.cpp')
0 files changed, 0 insertions, 0 deletions