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| author | Craig Topper <craig.topper@sifive.com> | 2021-12-10 09:27:13 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-12-10 09:35:51 -0800 |
| commit | 80ed2f6b3659d7d9449517a0eb552f361ce80e15 (patch) | |
| tree | cc586c281f3aad477e4f86acd21134efedb7aaaf /llvm/tools/llvm-readobj/llvm-readobj.cpp | |
| parent | c7c84b90879f0252c58894f70d2a19fc4c01cf64 (diff) | |
| download | llvm-80ed2f6b3659d7d9449517a0eb552f361ce80e15.zip llvm-80ed2f6b3659d7d9449517a0eb552f361ce80e15.tar.gz llvm-80ed2f6b3659d7d9449517a0eb552f361ce80e15.tar.bz2 | |
[RISCV] Share tablegen classes for F, D, and Zfh. Other simplifications. NFC
By adding the register class and funct as template parameters we
can share the classes with all 3 extensions.
I've used "let SchedRW =" to avoid repeating scheduler classes on
multiple lines where we previously inherited from the Sched class.
A subsequent patch will add mayRaiseFPException and FRM dependencies.
Reducing the number of classes means less repeating for those changes.
This of course conflicts with the Zfinx patch D93298.
Reviewed By: achieveartificialintelligence
Differential Revision: https://reviews.llvm.org/D115469
Diffstat (limited to 'llvm/tools/llvm-readobj/llvm-readobj.cpp')
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