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| author | Pablo Barrio <pablo.barrio@arm.com> | 2019-08-09 11:05:15 +0000 |
|---|---|---|
| committer | Pablo Barrio <pablo.barrio@arm.com> | 2019-08-09 11:05:15 +0000 |
| commit | 3cdd586be28f7dfe400f1186d1e3d8c31c625fb8 (patch) | |
| tree | 424dec3a9ed7d693e5bc844802dc763e75ba36f5 /llvm/tools/llvm-readobj/llvm-readobj.cpp | |
| parent | 5640860171e400fe4eb01816dc2a1a7d12afd1e2 (diff) | |
| download | llvm-3cdd586be28f7dfe400f1186d1e3d8c31c625fb8.zip llvm-3cdd586be28f7dfe400f1186d1e3d8c31c625fb8.tar.gz llvm-3cdd586be28f7dfe400f1186d1e3d8c31c625fb8.tar.bz2 | |
[AArch64] Set pref. func. align to 8 bytes on Neoverse E1 & Cortex-A65
Summary:
The Arm Neoverse E1 and Cortex-A65 Software Optimization Guide [1][2],
Section "4.7 Branch instruction alignment" state:
"It is preferable for branch targets, including subroutine entry points,
to be placed on aligned 64-bit boundaries to maximize instruction fetch
efficiency."
This patch sets the preferred function alignment on Neoverse E1 and
Cortex-A65 to 2^3=8B. This was already the case in some Cortex-A CPUs
such as Cortex-A53.
[1] https://developer.arm.com/docs/swog466751/latest/arm-neoversetm-e1-core-software-optimization-guide
[2] https://developer.arm.com/docs/swog010045/latest/arm-cortex-a65-core-software-optimization-guide
Reviewers: dmgreen, fhahn, samparker
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65937
llvm-svn: 368431
Diffstat (limited to 'llvm/tools/llvm-readobj/llvm-readobj.cpp')
0 files changed, 0 insertions, 0 deletions