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| author | Sander de Smalen <sander.desmalen@arm.com> | 2022-07-01 14:29:07 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2022-07-01 15:11:13 +0000 |
| commit | 690db164226fb1d454c5e592726a8bc0de16c6b5 (patch) | |
| tree | ee25e53d7dbb29f9a16942b42f7da22400c5f18e /llvm/tools/llvm-objdump/llvm-objdump.cpp | |
| parent | 560e694d48a6020f613281c29ffd17184f56dfb0 (diff) | |
| download | llvm-690db164226fb1d454c5e592726a8bc0de16c6b5.zip llvm-690db164226fb1d454c5e592726a8bc0de16c6b5.tar.gz llvm-690db164226fb1d454c5e592726a8bc0de16c6b5.tar.bz2 | |
[AArch64] Make nxv1i1 types a legal type for SVE.
One motivation to add support for these types are the LD1Q/ST1Q
instructions in SME, for which we have defined a number of load/store
intrinsics which at the moment still take a `<vscale x 16 x i1>` predicate
regardless of their element type.
This patch adds basic support for the nxv1i1 type such that it can be passed/returned
from functions, as well as some basic support to support some existing tests that
result in a nxv1i1 type. It also adds support for splats.
Other operations (e.g. insert/extract subvector, logical ops, etc) will be
supported in follow-up patches.
Reviewed By: paulwalker-arm, efriedma
Differential Revision: https://reviews.llvm.org/D128665
Diffstat (limited to 'llvm/tools/llvm-objdump/llvm-objdump.cpp')
0 files changed, 0 insertions, 0 deletions