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| author | Kamau Bridgeman <kamau.bridgeman.ibm@gmail.com> | 2023-07-14 13:05:32 -0500 |
|---|---|---|
| committer | Kamau Bridgeman <kamau.bridgeman.ibm@gmail.com> | 2023-07-14 13:38:40 -0500 |
| commit | 62c1cf7c63f0ef13e41c03de2c83590e6140e5fa (patch) | |
| tree | 79a9ed0ccf4ef4032d4a43e16f952caa3796445c /llvm/tools/llvm-objdump/llvm-objdump.cpp | |
| parent | 68d2814f421b0b584d7526d4bd095b6bbf585807 (diff) | |
| download | llvm-62c1cf7c63f0ef13e41c03de2c83590e6140e5fa.zip llvm-62c1cf7c63f0ef13e41c03de2c83590e6140e5fa.tar.gz llvm-62c1cf7c63f0ef13e41c03de2c83590e6140e5fa.tar.bz2 | |
[PowerPC][Future] Enable __builtin_mma_xxm[t|f]acc
Future cpu instructions dmxxinstdmr512 and dmxxextfdmr512 insert and extract
quad vectors from the new wide accumulator(wacc) register class.
The introduction of these new instructions renders the p10 instructions
xxmtacc and xxmfacc obsolete since the new wacc register class is a better
choice for handing quad vector operations. This patch ensures that, for
future cpu, instructions dmxxinstdmr512 and dmxxextfdmr512 are generated
by custom lowering the intrinsics for xxm[t|f]acc to produce no instructions.
Reviewed By: amyk, lei
Differential Revision: https://reviews.llvm.org/D153034
Diffstat (limited to 'llvm/tools/llvm-objdump/llvm-objdump.cpp')
0 files changed, 0 insertions, 0 deletions