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author | David Green <david.green@arm.com> | 2022-05-16 18:00:30 +0100 |
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committer | David Green <david.green@arm.com> | 2022-05-16 18:00:30 +0100 |
commit | 5d29d752735e71b73a54bfc9ab747384be9e4246 (patch) | |
tree | dab9082baa18e2e6f10ef1782454167a339bcd0d /llvm/tools/llvm-objdump/llvm-objdump.cpp | |
parent | 3794cc0e996481e10307b67c8436aa44e0d65d22 (diff) | |
download | llvm-5d29d752735e71b73a54bfc9ab747384be9e4246.zip llvm-5d29d752735e71b73a54bfc9ab747384be9e4246.tar.gz llvm-5d29d752735e71b73a54bfc9ab747384be9e4246.tar.bz2 |
[AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32
There have been some patterns in the AArch64 backend to optimize code of
the form:
ldrsh w8, [x0]
scvtf s0, w8
to:
ldr h0, [x0]
sshll v0.4s, v0.4h, #0
scvtf s0, s0
The idea is to remove the GRP->FPR move, but in reality is making code
larger and slower (or the same) on all the cpus I tried.
This patch adds the UseAlternateSExtLoadCVTF32 predicate similar to
nearby related pattern.
Differential Revision: https://reviews.llvm.org/D125470
Diffstat (limited to 'llvm/tools/llvm-objdump/llvm-objdump.cpp')
0 files changed, 0 insertions, 0 deletions