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authorCraig Topper <craig.topper@sifive.com>2021-07-28 08:57:02 -0700
committerCraig Topper <craig.topper@sifive.com>2021-07-28 09:05:45 -0700
commit54588bcc052e5b08f90e672c33d0c1ad4eda2424 (patch)
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parent4e65688571221565cf1a5c1e4bb58ee2ab7c9c83 (diff)
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[RISCV] Restrict performANY_EXTENDCombine to prevent an infinite loop.
The sign_extend we insert here can get turned into a zero_extend if the sign bit is known zero. This can enable a setcc combine that shrinks compares with zero_extend. This reduces the use count of the zero_extend allowing other combines to turn it back into an any_extend. This restricts the combine to only cases where the result is used by a CopyToReg. This works for my original motivating case. I hope the CopyToReg use will prevent any converted extends from turning back into an any_extend. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D106754
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