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authorPhilipp Tomsich <philipp.tomsich@vrull.eu>2024-02-09 15:48:46 -0800
committerGitHub <noreply@github.com>2024-02-10 00:48:46 +0100
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[AArch64] Add Ampere1B scheduling/pipeline model (#81338)
The Ampere1B core is enabled with a new scheduling/pipeline model, as it provides significant updates over the Ampere1 core; it reduces latencies on many instructions, has some micro-ops reassigned between the XY and X units, and provides modelling for the instructions added since Ampere1 and Ampere1A.
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