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| author | Djordje Todorovic <djordje.todorovic@htecgroup.com> | 2025-03-07 09:21:36 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-07 09:21:36 +0100 |
| commit | 5048a0858beb15bdd203dee89dd4df9b2a72ba5f (patch) | |
| tree | 27b0c13f3ade106e655b02bed5b38ce4703f3b67 /llvm/tools/llvm-objcopy/llvm-objcopy.cpp | |
| parent | 749d68bdfe97c6dd29fb9f7e4a7f63854ecef295 (diff) | |
| download | llvm-5048a0858beb15bdd203dee89dd4df9b2a72ba5f.zip llvm-5048a0858beb15bdd203dee89dd4df9b2a72ba5f.tar.gz llvm-5048a0858beb15bdd203dee89dd4df9b2a72ba5f.tar.bz2 | |
[RISCV] Generate MIPS load/store pair instructions (#124717)
Introduce RISCVLoadStoreOptimizer MIR Pass that will do the
optimization. The load/store pairing pass identifies adjacent load/store
instructions operating on consecutive memory locations and merges them
into a single paired instruction.
This is part of MIPS extensions for the p8700 CPU.
Production of ldp/sdp instructions is OFF by default, since it is
beneficial for -Os only in the case of p8700 CPU.
Diffstat (limited to 'llvm/tools/llvm-objcopy/llvm-objcopy.cpp')
0 files changed, 0 insertions, 0 deletions