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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2019-02-11 09:37:42 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2019-02-11 09:37:42 +0000 |
| commit | 150ccb889e9e4d7a029d80e061f45570c95dd309 (patch) | |
| tree | 8796fa68b2a6f529fb559b8d550d47314c1d894d /llvm/tools/llvm-objcopy/llvm-objcopy.cpp | |
| parent | 734648bb4affcecbf3435c8c8f8459968abce577 (diff) | |
| download | llvm-150ccb889e9e4d7a029d80e061f45570c95dd309.zip llvm-150ccb889e9e4d7a029d80e061f45570c95dd309.tar.gz llvm-150ccb889e9e4d7a029d80e061f45570c95dd309.tar.bz2 | |
[ARM] LoadStoreOptimizer: reoder limit
The whole design of generating LDMs/STMs is fragile and unreliable: it depends on
rescheduling here in the LoadStoreOptimizer that isn't register pressure aware
and regalloc that isn't aware of generating LDMs/STMs.
This patch adds a (hidden) option to control the total number of instructions that
can be re-ordered. I appreciate this looks only a tiny bit better than a hard-coded
constant, but at least it allows more easy experimentation with different values
for now. Ideally we calculate this reorder limit based on some heuristics, and take
register pressure into account. I might be looking into that next.
Differential Revision: https://reviews.llvm.org/D57954
llvm-svn: 353678
Diffstat (limited to 'llvm/tools/llvm-objcopy/llvm-objcopy.cpp')
0 files changed, 0 insertions, 0 deletions