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| author | Jordan Rupprecht <rupprecht@google.com> | 2019-04-30 15:21:36 +0000 |
|---|---|---|
| committer | Jordan Rupprecht <rupprecht@google.com> | 2019-04-30 15:21:36 +0000 |
| commit | 96bbb1dc2b390f1ed17152c77a7476f898ebcd0c (patch) | |
| tree | 9f71493a555f420bca007ee73e32f88f2f9c0bd3 /llvm/tools/llvm-objcopy/CopyConfig.cpp | |
| parent | 21c31f5e7b30f3eaf14a2e79b952fb389174065c (diff) | |
| download | llvm-96bbb1dc2b390f1ed17152c77a7476f898ebcd0c.zip llvm-96bbb1dc2b390f1ed17152c77a7476f898ebcd0c.tar.gz llvm-96bbb1dc2b390f1ed17152c77a7476f898ebcd0c.tar.bz2 | |
[llvm-objcopy] Add RISC-V support for -B/-O
Reviewers: jorgbrown, espindola, alexshap, jhenderson
Subscribers: emaste, arichardson, fedor.sergeev, jakehehrlich, kito-cheng, shiva0217, MaskRay, rogfer01, rkruppe, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61272
llvm-svn: 359568
Diffstat (limited to 'llvm/tools/llvm-objcopy/CopyConfig.cpp')
| -rw-r--r-- | llvm/tools/llvm-objcopy/CopyConfig.cpp | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/llvm/tools/llvm-objcopy/CopyConfig.cpp b/llvm/tools/llvm-objcopy/CopyConfig.cpp index 1b9e4148..ddb8d4d 100644 --- a/llvm/tools/llvm-objcopy/CopyConfig.cpp +++ b/llvm/tools/llvm-objcopy/CopyConfig.cpp @@ -260,6 +260,8 @@ static const StringMap<MachineInfo> ArchMap{ {"i386:x86-64", {ELF::EM_X86_64, true, true}}, {"mips", {ELF::EM_MIPS, false, false}}, {"powerpc:common64", {ELF::EM_PPC64, true, true}}, + {"riscv:rv32", {ELF::EM_RISCV, false, true}}, + {"riscv:rv64", {ELF::EM_RISCV, true, true}}, {"sparc", {ELF::EM_SPARC, false, true}}, {"x86-64", {ELF::EM_X86_64, true, true}}, }; @@ -275,22 +277,31 @@ static Expected<const MachineInfo &> getMachineInfo(StringRef Arch) { // FIXME: consolidate with the bfd parsing used by lld. static const StringMap<MachineInfo> OutputFormatMap{ // Name, {EMachine, 64bit, LittleEndian} + // x86 {"elf32-i386", {ELF::EM_386, false, true}}, + {"elf32-x86-64", {ELF::EM_X86_64, false, true}}, + {"elf64-x86-64", {ELF::EM_X86_64, true, true}}, + // Intel MCU {"elf32-iamcu", {ELF::EM_IAMCU, false, true}}, + // ARM {"elf32-littlearm", {ELF::EM_ARM, false, true}}, - {"elf32-x86-64", {ELF::EM_X86_64, false, true}}, + // ARM AArch64 {"elf64-aarch64", {ELF::EM_AARCH64, true, true}}, {"elf64-littleaarch64", {ELF::EM_AARCH64, true, true}}, + // RISC-V + {"elf32-littleriscv", {ELF::EM_RISCV, false, true}}, + {"elf64-littleriscv", {ELF::EM_RISCV, true, true}}, + // PowerPC {"elf32-powerpc", {ELF::EM_PPC, false, false}}, {"elf32-powerpcle", {ELF::EM_PPC, false, true}}, {"elf64-powerpc", {ELF::EM_PPC64, true, false}}, {"elf64-powerpcle", {ELF::EM_PPC64, true, true}}, - {"elf64-x86-64", {ELF::EM_X86_64, true, true}}, - {"elf32-tradbigmips", {ELF::EM_MIPS, false, false}}, + // MIPS {"elf32-bigmips", {ELF::EM_MIPS, false, false}}, {"elf32-ntradbigmips", {ELF::EM_MIPS, false, false}}, - {"elf32-tradlittlemips", {ELF::EM_MIPS, false, true}}, {"elf32-ntradlittlemips", {ELF::EM_MIPS, false, true}}, + {"elf32-tradbigmips", {ELF::EM_MIPS, false, false}}, + {"elf32-tradlittlemips", {ELF::EM_MIPS, false, true}}, {"elf64-tradbigmips", {ELF::EM_MIPS, true, false}}, {"elf64-tradlittlemips", {ELF::EM_MIPS, true, true}}, }; |