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| author | Petar Avramovic <Petar.Avramovic@amd.com> | 2022-04-21 15:41:12 +0200 |
|---|---|---|
| committer | Petar Avramovic <Petar.Avramovic@amd.com> | 2022-04-21 16:12:04 +0200 |
| commit | e06290e53f2880962fef582f118482d70f1c27f0 (patch) | |
| tree | 0774266e9d665f63de637c6a053d93c523769d4a /llvm/tools/llvm-ml/llvm-ml.cpp | |
| parent | 4e0dacb2cf325158c3c672f45202ab166aec99b0 (diff) | |
| download | llvm-e06290e53f2880962fef582f118482d70f1c27f0.zip llvm-e06290e53f2880962fef582f118482d70f1c27f0.tar.gz llvm-e06290e53f2880962fef582f118482d70f1c27f0.tar.bz2 | |
AMDGPU/GlobalISel: Fix isVCC for uniform s1 with reg class on wave32
Fix isVCC for register that was assigned register class during
inst-selection. This happens when register has multiple uses.
For wave32, uniform i1 to vcc copy was selected like vcc to vcc
copy when uniform i1 had assigned register class.
Uniform i1 register with assigned register class will have s1 LLT,
be defined using G_TRUNC and class will be SReg_32RegClass.
Vcc i1 register with assigned register class will have s1 LLT,
class will be SReg_32RegClass for wave32 and SReg_64RegClass for
wave64 and register will not be defined by G_TRUNC.
Differential Revision: https://reviews.llvm.org/D124163
Diffstat (limited to 'llvm/tools/llvm-ml/llvm-ml.cpp')
0 files changed, 0 insertions, 0 deletions