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| author | Simon Tatham <simon.tatham@arm.com> | 2020-01-20 13:25:50 +0000 |
|---|---|---|
| committer | Simon Tatham <simon.tatham@arm.com> | 2020-01-20 13:25:52 +0000 |
| commit | f3e73e88fdd63e3342977873a5f2c3f870a2497a (patch) | |
| tree | 5ea63dd7f4f762079ec418c3f456000bc9b80a03 /llvm/tools/llvm-ml/Disassembler.cpp | |
| parent | 01bfb366acf3650b91a80b922f2fc7b6e660f686 (diff) | |
| download | llvm-f3e73e88fdd63e3342977873a5f2c3f870a2497a.zip llvm-f3e73e88fdd63e3342977873a5f2c3f870a2497a.tar.gz llvm-f3e73e88fdd63e3342977873a5f2c3f870a2497a.tar.bz2 | |
[ARM,MVE] Fix confusing MC names for MVE VMINA/VMAXA insns.
Summary:
A recent commit accidentally defined names like `MVE_VMAXAs8` as
instances of the multiclass `MVE_VMINA`, and vice versa. This has no
effect on the test suite, because nothing directly refers to those
instruction names (the isel patterns are generated in Tablegen using
`!cast<Instruction>(NAME)` inside a lower-level multiclass). But it
means that `llvm-mc -show-inst` was listing VMAXA as VMINA, and it
would also affect any further draft code gen patches that use those
instruction ids.
Reviewers: MarkMurrayARM, dmgreen, miyuki, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73034
Diffstat (limited to 'llvm/tools/llvm-ml/Disassembler.cpp')
0 files changed, 0 insertions, 0 deletions