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| author | Andrzej Warzynski <andrzej.warzynski@arm.com> | 2020-01-17 12:04:07 +0000 |
|---|---|---|
| committer | Andrzej Warzynski <andrzej.warzynski@arm.com> | 2020-01-20 12:19:18 +0000 |
| commit | 7e717b3990554f0fde43e3747529477a70072cfe (patch) | |
| tree | 9335089804eb807c7b2ecbd7430c9035e9b18109 /llvm/tools/llvm-ml/Disassembler.cpp | |
| parent | 468ca490c6030462066f8e731902d81bab11c356 (diff) | |
| download | llvm-7e717b3990554f0fde43e3747529477a70072cfe.zip llvm-7e717b3990554f0fde43e3747529477a70072cfe.tar.gz llvm-7e717b3990554f0fde43e3747529477a70072cfe.tar.bz2 | |
[AArch64][SVE] Extend int_aarch64_sve_ld1_gather_imm
The ACLE distinguishes between the following addressing modes for gather
loads:
* "scalar base, vector offset", and
* "vector base, scalar offset".
For the "vector base, scalar offset" case, the
`int_aarch64_sve_ld1_gather_imm` intrinsic was added in 79f2422d.
Currently, that intrinsic assumes that the scalar offset is passed as an
immediate. As a result, it does not cater for cases where scalar offset
is stored in a register.
In this patch `int_aarch64_sve_ld1_gather_imm` is extended so that all
cases are covered:
* `int_aarch64_sve_ld1_gather_imm` is renamed as
`int_aarch64_sve_ld1_gather_scalar_offset`
* new DAG combine rules are added for GLD1_IMM for scenarios where the
offset is a non-immediate scalar or an out-of-range immediate
* sve-intrinsics-gather-loads-vector-base.ll is renamed as
sve-intrinsics-gather-loads-vector-base-imm-offset.ll
* sve-intrinsics-gather-loads-vector-base-scalar-offset.ll is added to test
file for non-immediate offsets
Similar changes are made for scatter store intrinsics.
Reviewed By: sdesmalen, efriedma
Differential Revision: https://reviews.llvm.org/D71773
Diffstat (limited to 'llvm/tools/llvm-ml/Disassembler.cpp')
0 files changed, 0 insertions, 0 deletions