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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-07-31 13:48:58 -0400 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-08-14 13:18:03 -0400 |
| commit | 40a142fa57d648e3daadfdaa75731360e1ebab2e (patch) | |
| tree | ba1acbf80b480e9651a73d3ad3ce11ea8d246145 /llvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp | |
| parent | b6db0a544df1f28e7fa53b74e19839e55e63c8c9 (diff) | |
| download | llvm-40a142fa57d648e3daadfdaa75731360e1ebab2e.zip llvm-40a142fa57d648e3daadfdaa75731360e1ebab2e.tar.gz llvm-40a142fa57d648e3daadfdaa75731360e1ebab2e.tar.bz2 | |
AMDGPU/GlobalISel: Match andn2/orn2 for more types
Unfortunately this ends up not working as expected on targets with
16-bit operations due to AMDGPUCodeGenPrepare's promotion of uniform
16-bit ops to i32.
The vector case annoyingly requires switching the checked opcode,
since constants for vectors aren't directly handled.
I also need to think more carefully about whether this is valid for i1.
Diffstat (limited to 'llvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp')
0 files changed, 0 insertions, 0 deletions