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| author | Craig Topper <craig.topper@sifive.com> | 2025-04-24 08:27:38 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-24 08:27:38 -0700 |
| commit | 2ca071b1decf006a31385c75478b57013964e49a (patch) | |
| tree | b24d11e8e034186310406f9dda255cdc29167de2 /llvm/tools/llvm-cov/CodeCoverage.cpp | |
| parent | a903c7b7f5d1cb8d72c170d494d94dc251fc7204 (diff) | |
| download | llvm-2ca071b1decf006a31385c75478b57013964e49a.zip llvm-2ca071b1decf006a31385c75478b57013964e49a.tar.gz llvm-2ca071b1decf006a31385c75478b57013964e49a.tar.bz2 | |
[TableGen][RISCV][AArch64][GISel] Properly implement isAnyExtLoad/isSignExtLoad/isZeroExtLoad for IsAtomic in SelectionDAG. (#137096)
Support isAnyExtLoad() for IsAtomic in GISel.
Modify atomic_load_az* to check for extload or zextload. And rename to
atomic_load_azext*
Add atomic_load_asext* and use in RISC-V. I used "asext" rather than
"as" so it wouldn't be confused with the word "as".
Diffstat (limited to 'llvm/tools/llvm-cov/CodeCoverage.cpp')
0 files changed, 0 insertions, 0 deletions