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| author | Igor Wodiany <igor.wodiany@imgtec.com> | 2025-10-28 10:47:23 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-28 10:47:23 +0000 |
| commit | 21ab523bf64dabd3ce4246daf992d1033fec81bd (patch) | |
| tree | aceff29c257955f98babcefb66c49b31585b352b /llvm/test/DebugInfo/WebAssembly | |
| parent | 7bb0d96e87e0129b960bb6a0a89de1a9a38f9f95 (diff) | |
| download | llvm-main.zip llvm-main.tar.gz llvm-main.tar.bz2 | |
The Intel Cache Control tests are separated and not validated as
`spirv-val` fails with: "ID '7' decorated with CacheControlLoadINTEL
multiple times is not allowed". However, Intel extension does allow
duplicated decoration if cache level in each annotation is different. It
seems that `spirv-val` does not currently support it.
Diffstat (limited to 'llvm/test/DebugInfo/WebAssembly')
0 files changed, 0 insertions, 0 deletions