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| author | RolandF77 <55763885+RolandF77@users.noreply.github.com> | 2024-10-21 12:19:07 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-21 12:19:07 -0400 |
| commit | fc59f2cc0f191bb7a0706dfb65e3e46fef69f466 (patch) | |
| tree | 1af04cab59bae7f73f178341bca920ade3e07e46 /llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll | |
| parent | 54c93aabec965469fe7db1f4391a190e3d640feb (diff) | |
| download | llvm-fc59f2cc0f191bb7a0706dfb65e3e46fef69f466.zip llvm-fc59f2cc0f191bb7a0706dfb65e3e46fef69f466.tar.gz llvm-fc59f2cc0f191bb7a0706dfb65e3e46fef69f466.tar.bz2 | |
[PowerPC] special case small int constant for custom scalar_to_vector (#109850)
Special case small int constant in the PPC custom lowering of
scalar_to_vector.
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll | 80 |
1 files changed, 30 insertions, 50 deletions
diff --git a/llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll b/llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll index fba6725..2259b6e 100644 --- a/llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll +++ b/llvm/test/CodeGen/PowerPC/build-vector-from-load-and-zeros.ll @@ -26,18 +26,14 @@ define <2 x i64> @build_v2i64_extload_0(ptr nocapture noundef readonly %p) { ; ; PWR7-LE-LABEL: build_v2i64_extload_0: ; PWR7-LE: # %bb.0: # %entry -; PWR7-LE-NEXT: li 4, 0 -; PWR7-LE-NEXT: stw 4, -16(1) -; PWR7-LE-NEXT: addis 4, 2, .LCPI0_0@toc@ha ; PWR7-LE-NEXT: lfiwzx 0, 0, 3 -; PWR7-LE-NEXT: addi 3, 1, -16 -; PWR7-LE-NEXT: addi 4, 4, .LCPI0_0@toc@l -; PWR7-LE-NEXT: lxvd2x 1, 0, 4 -; PWR7-LE-NEXT: xxspltw 35, 0, 1 +; PWR7-LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; PWR7-LE-NEXT: xxlxor 36, 36, 36 +; PWR7-LE-NEXT: addi 3, 3, .LCPI0_0@toc@l +; PWR7-LE-NEXT: xxspltw 34, 0, 1 ; PWR7-LE-NEXT: lxvd2x 0, 0, 3 -; PWR7-LE-NEXT: xxswapd 34, 1 -; PWR7-LE-NEXT: xxswapd 36, 0 -; PWR7-LE-NEXT: vperm 2, 4, 3, 2 +; PWR7-LE-NEXT: xxswapd 35, 0 +; PWR7-LE-NEXT: vperm 2, 4, 2, 3 ; PWR7-LE-NEXT: blr ; ; PWR8-LE-LABEL: build_v2i64_extload_0: @@ -357,18 +353,14 @@ define <4 x i32> @build_v4i32_load_0(ptr nocapture noundef readonly %p) { ; ; PWR7-LE-LABEL: build_v4i32_load_0: ; PWR7-LE: # %bb.0: # %entry -; PWR7-LE-NEXT: li 4, 0 -; PWR7-LE-NEXT: stw 4, -16(1) -; PWR7-LE-NEXT: addis 4, 2, .LCPI8_0@toc@ha ; PWR7-LE-NEXT: lfiwzx 0, 0, 3 -; PWR7-LE-NEXT: addi 3, 1, -16 -; PWR7-LE-NEXT: addi 4, 4, .LCPI8_0@toc@l -; PWR7-LE-NEXT: lxvd2x 1, 0, 4 -; PWR7-LE-NEXT: xxspltw 35, 0, 1 +; PWR7-LE-NEXT: addis 3, 2, .LCPI8_0@toc@ha +; PWR7-LE-NEXT: xxlxor 36, 36, 36 +; PWR7-LE-NEXT: addi 3, 3, .LCPI8_0@toc@l +; PWR7-LE-NEXT: xxspltw 34, 0, 1 ; PWR7-LE-NEXT: lxvd2x 0, 0, 3 -; PWR7-LE-NEXT: xxswapd 34, 1 -; PWR7-LE-NEXT: xxswapd 36, 0 -; PWR7-LE-NEXT: vperm 2, 4, 3, 2 +; PWR7-LE-NEXT: xxswapd 35, 0 +; PWR7-LE-NEXT: vperm 2, 4, 2, 3 ; PWR7-LE-NEXT: blr ; ; PWR8-LE-LABEL: build_v4i32_load_0: @@ -412,18 +404,14 @@ define <4 x i32> @build_v4i32_load_1(ptr nocapture noundef readonly %p) { ; ; PWR7-LE-LABEL: build_v4i32_load_1: ; PWR7-LE: # %bb.0: # %entry -; PWR7-LE-NEXT: li 4, 0 -; PWR7-LE-NEXT: stw 4, -16(1) -; PWR7-LE-NEXT: addis 4, 2, .LCPI9_0@toc@ha ; PWR7-LE-NEXT: lfiwzx 0, 0, 3 -; PWR7-LE-NEXT: addi 3, 1, -16 -; PWR7-LE-NEXT: addi 4, 4, .LCPI9_0@toc@l -; PWR7-LE-NEXT: lxvd2x 1, 0, 4 -; PWR7-LE-NEXT: xxspltw 35, 0, 1 +; PWR7-LE-NEXT: addis 3, 2, .LCPI9_0@toc@ha +; PWR7-LE-NEXT: xxlxor 36, 36, 36 +; PWR7-LE-NEXT: addi 3, 3, .LCPI9_0@toc@l +; PWR7-LE-NEXT: xxspltw 34, 0, 1 ; PWR7-LE-NEXT: lxvd2x 0, 0, 3 -; PWR7-LE-NEXT: xxswapd 34, 1 -; PWR7-LE-NEXT: xxswapd 36, 0 -; PWR7-LE-NEXT: vperm 2, 3, 4, 2 +; PWR7-LE-NEXT: xxswapd 35, 0 +; PWR7-LE-NEXT: vperm 2, 2, 4, 3 ; PWR7-LE-NEXT: blr ; ; PWR8-LE-LABEL: build_v4i32_load_1: @@ -469,18 +457,14 @@ define <4 x i32> @build_v4i32_load_2(ptr nocapture noundef readonly %p) { ; ; PWR7-LE-LABEL: build_v4i32_load_2: ; PWR7-LE: # %bb.0: # %entry -; PWR7-LE-NEXT: li 4, 0 -; PWR7-LE-NEXT: stw 4, -16(1) -; PWR7-LE-NEXT: addis 4, 2, .LCPI10_0@toc@ha ; PWR7-LE-NEXT: lfiwzx 0, 0, 3 -; PWR7-LE-NEXT: addi 3, 1, -16 -; PWR7-LE-NEXT: addi 4, 4, .LCPI10_0@toc@l -; PWR7-LE-NEXT: lxvd2x 1, 0, 4 -; PWR7-LE-NEXT: xxspltw 35, 0, 1 +; PWR7-LE-NEXT: addis 3, 2, .LCPI10_0@toc@ha +; PWR7-LE-NEXT: xxlxor 36, 36, 36 +; PWR7-LE-NEXT: addi 3, 3, .LCPI10_0@toc@l +; PWR7-LE-NEXT: xxspltw 34, 0, 1 ; PWR7-LE-NEXT: lxvd2x 0, 0, 3 -; PWR7-LE-NEXT: xxswapd 34, 1 -; PWR7-LE-NEXT: xxswapd 36, 0 -; PWR7-LE-NEXT: vperm 2, 3, 4, 2 +; PWR7-LE-NEXT: xxswapd 35, 0 +; PWR7-LE-NEXT: vperm 2, 2, 4, 3 ; PWR7-LE-NEXT: blr ; ; PWR8-LE-LABEL: build_v4i32_load_2: @@ -524,18 +508,14 @@ define <4 x i32> @build_v4i32_load_3(ptr nocapture noundef readonly %p) { ; ; PWR7-LE-LABEL: build_v4i32_load_3: ; PWR7-LE: # %bb.0: # %entry -; PWR7-LE-NEXT: li 4, 0 -; PWR7-LE-NEXT: stw 4, -16(1) -; PWR7-LE-NEXT: addis 4, 2, .LCPI11_0@toc@ha ; PWR7-LE-NEXT: lfiwzx 0, 0, 3 -; PWR7-LE-NEXT: addi 3, 1, -16 -; PWR7-LE-NEXT: addi 4, 4, .LCPI11_0@toc@l -; PWR7-LE-NEXT: lxvd2x 1, 0, 4 -; PWR7-LE-NEXT: xxspltw 35, 0, 1 +; PWR7-LE-NEXT: addis 3, 2, .LCPI11_0@toc@ha +; PWR7-LE-NEXT: xxlxor 36, 36, 36 +; PWR7-LE-NEXT: addi 3, 3, .LCPI11_0@toc@l +; PWR7-LE-NEXT: xxspltw 34, 0, 1 ; PWR7-LE-NEXT: lxvd2x 0, 0, 3 -; PWR7-LE-NEXT: xxswapd 34, 1 -; PWR7-LE-NEXT: xxswapd 36, 0 -; PWR7-LE-NEXT: vperm 2, 3, 4, 2 +; PWR7-LE-NEXT: xxswapd 35, 0 +; PWR7-LE-NEXT: vperm 2, 2, 4, 3 ; PWR7-LE-NEXT: blr ; ; PWR8-LE-LABEL: build_v4i32_load_3: |