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| author | Hsiangkai Wang <kai.wang@sifive.com> | 2021-03-15 13:58:11 +0800 |
|---|---|---|
| committer | Hsiangkai Wang <kai.wang@sifive.com> | 2021-03-19 07:46:16 +0800 |
| commit | aa8d33a6d6346e1ed444a59d0655f4a43ba96875 (patch) | |
| tree | c5eaed813d658dae530e9c3f6cf8ce6a85f6f542 /llvm/lib/Transforms/Utils/SimplifyIndVar.cpp | |
| parent | 9558456b5370e64560e76f6580b979fccadd4744 (diff) | |
| download | llvm-aa8d33a6d6346e1ed444a59d0655f4a43ba96875.zip llvm-aa8d33a6d6346e1ed444a59d0655f4a43ba96875.tar.gz llvm-aa8d33a6d6346e1ed444a59d0655f4a43ba96875.tar.bz2 | |
[RISCV] Spilling for Zvlsseg registers.
For Zvlsseg, we create several tuple register classes. When spilling for
these tuple register classes, we need to iterate NF times to load/store
these tuple registers.
Differential Revision: https://reviews.llvm.org/D98629
Diffstat (limited to 'llvm/lib/Transforms/Utils/SimplifyIndVar.cpp')
0 files changed, 0 insertions, 0 deletions