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| author | Kito Cheng <kito.cheng@sifive.com> | 2022-07-08 17:00:53 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-07-08 17:01:22 +0800 |
| commit | 7b9a3b9d6d98184d3e20c03fceefaac6dc0c3580 (patch) | |
| tree | abc243703a5e05fc2dab9cb062053fda6d84d77f /llvm/lib/Transforms/Utils/SimplifyIndVar.cpp | |
| parent | a59c3eb2f37d4c8d0a8e48a698cec9314c7f4853 (diff) | |
| download | llvm-7b9a3b9d6d98184d3e20c03fceefaac6dc0c3580.zip llvm-7b9a3b9d6d98184d3e20c03fceefaac6dc0c3580.tar.gz llvm-7b9a3b9d6d98184d3e20c03fceefaac6dc0c3580.tar.bz2 | |
[RISCV] Precommit testcase to show wrong result of make-compressible optimization
Use following example to demo what happened now:
li a1, 1
sd a1, 800(a0)
sd a0, 808(a0) # Store base address into base + offset
li a1, 2
sd a1, 816(a0)
Current will optimizate into:
li a1, 1
addi a2, a0, 768
sd a1, 32(a2)
sd a2, 40(a2) # Wrong replacement for the source register.
li a1, 2
sd a1, 48(a2)
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D128875
Diffstat (limited to 'llvm/lib/Transforms/Utils/SimplifyIndVar.cpp')
0 files changed, 0 insertions, 0 deletions