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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-21 13:23:45 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-02-12 09:35:10 -0500 |
| commit | fa61e200e53aaa929276abd76482a15c7a9638b7 (patch) | |
| tree | 96de685fc12b0f506259a15643484d9cd7fda3c1 /llvm/lib/Transforms/Utils/SimplifyCFG.cpp | |
| parent | 271e495399170d69627c1acd591c9298cb0b5b4b (diff) | |
| download | llvm-fa61e200e53aaa929276abd76482a15c7a9638b7.zip llvm-fa61e200e53aaa929276abd76482a15c7a9638b7.tar.gz llvm-fa61e200e53aaa929276abd76482a15c7a9638b7.tar.bz2 | |
AMDGPU/GlobalISel: Widen non-power-of-2 load results
Load extra bits if suitably aligned. This allows using widened
3-vector loads on SI, and fixes legalization for <9 x s32> (which LSV
apparently forms frequently on lowered kernel argument lists).
Fix incorrectly treating these as legal on SI. This should emit a
64-bit store and a 32-bit store.
I think all of the load and store rules are just about complete, but
due for a rewrite.
Diffstat (limited to 'llvm/lib/Transforms/Utils/SimplifyCFG.cpp')
0 files changed, 0 insertions, 0 deletions