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| author | Craig Topper <craig.topper@sifive.com> | 2024-08-02 09:02:58 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-02 09:02:58 -0700 |
| commit | 4aac78dd4a89f16657c162320e3a720437cb7284 (patch) | |
| tree | 738554fa9ab7b9d85cfc8c7ad8f4bf2c80a8df1d /llvm/lib/Transforms/Utils/SimplifyCFG.cpp | |
| parent | 9d07f43676f03460d913aabd503ae8154cabdda1 (diff) | |
| download | llvm-4aac78dd4a89f16657c162320e3a720437cb7284.zip llvm-4aac78dd4a89f16657c162320e3a720437cb7284.tar.gz llvm-4aac78dd4a89f16657c162320e3a720437cb7284.tar.bz2 | |
[RISCV] Generalize existing SRA combine to fix #101040. (#101610)
We already had a DAG combine for (sra (sext_inreg (shl X, C1), i32), C2)
-> (sra (shl X, C1+32), C2+32) that we used for RV64. This patch
generalizes it to other sext_inregs for both RV32 and RV64.
Fixes #101040.
Diffstat (limited to 'llvm/lib/Transforms/Utils/SimplifyCFG.cpp')
0 files changed, 0 insertions, 0 deletions