diff options
| author | David Sherwood <david.sherwood@arm.com> | 2025-09-08 10:34:53 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-08 10:34:53 +0100 |
| commit | dd0161f6025bb97f6784e0bc7e1b5849acae44dd (patch) | |
| tree | 3fdad8b966be3429cef4aa7a2a8ab2c4dda63483 /llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp | |
| parent | c71da7d5e0f63e7158c1260dfac034896150b669 (diff) | |
| download | llvm-dd0161f6025bb97f6784e0bc7e1b5849acae44dd.zip llvm-dd0161f6025bb97f6784e0bc7e1b5849acae44dd.tar.gz llvm-dd0161f6025bb97f6784e0bc7e1b5849acae44dd.tar.bz2 | |
[AArch64] Improve lowering for scalable masked interleaving stores (#156718)
Similar to #154338, this PR aims to support lowering of certain IR
to SVE's st2 and st4 instructions. The typical IR scenario looks
like:
%mask = .. @llvm.vector.interleave2(<vscale x 16 x i1> %m, <vscale x 16
x i1> %m)
%val = .. @llvm.vector.interleave2(<vscale x 16 x i8> %v1, <vscale x 16
x i8> %v2)
.. @llvm.masked.store.nxv32i8.p0(<vscale x 32 x i8> %val, ..., <vscale x
32 x i1> %mask)
where we're interleaving both the value and the mask being passed
to the wide store. When the mask interleave parts are identical
we can lower this to st2b.
This PR adds a DAG combine for lowering this kind of IR pattern
to st2X and st4X SVE instructions.
Diffstat (limited to 'llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp')
0 files changed, 0 insertions, 0 deletions