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| author | Matt Devereau <matthew.devereau@arm.com> | 2023-08-09 15:37:51 +0000 |
|---|---|---|
| committer | Matt Devereau <matthew.devereau@arm.com> | 2023-08-11 14:48:19 +0000 |
| commit | c52d9509d40d3048914b144618232213e6076e05 (patch) | |
| tree | c42264333d90aef55ac12b9be527080e3327361c /llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp | |
| parent | b108c11e4656c695853a14032ba33671a676203e (diff) | |
| download | llvm-c52d9509d40d3048914b144618232213e6076e05.zip llvm-c52d9509d40d3048914b144618232213e6076e05.tar.gz llvm-c52d9509d40d3048914b144618232213e6076e05.tar.bz2 | |
[AArch64][SVE] Add asm predicate constraint Uph
Some instructions such as multi-vector LD1 only accept a range
of PN8-PN15 predicate-as-counter. This new constraint allows more
refined parsing and better decision making when parsing these
instructions from ASM, instead of defaulting to Upa which incorrectly
uses the whole range of registers P0-P15 from the register class PPR.
Differential Revision: https://reviews.llvm.org/D157517
Diffstat (limited to 'llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp')
0 files changed, 0 insertions, 0 deletions