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| author | Sanjay Patel <spatel@rotateright.com> | 2016-04-12 23:16:23 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-04-12 23:16:23 +0000 |
| commit | 5e5056d93971a6dae6918a5869d348962fab2fa2 (patch) | |
| tree | ec26dc088e8af2c7eb315d075502d0477c82b29e /llvm/lib/Transforms/Utils/NameAnonFunctions.cpp | |
| parent | 2d3690bc986c9d852ffd96f96ba274750ef084b3 (diff) | |
| download | llvm-5e5056d93971a6dae6918a5869d348962fab2fa2.zip llvm-5e5056d93971a6dae6918a5869d348962fab2fa2.tar.gz llvm-5e5056d93971a6dae6918a5869d348962fab2fa2.tar.bz2 | |
[x86, InstCombine] fix masked load pass-through operand to be a zero vector
This bug was introduced with:
http://reviews.llvm.org/rL262269
AVX masked loads are specified to set vector lanes to zero when the high bit of the mask
element for that lane is zero:
"If the mask is 0, the corresponding data element is set to zero in the load form of these
instructions, and unmodified in the store form." --Intel manual
Differential Revision: http://reviews.llvm.org/D19017
llvm-svn: 266148
Diffstat (limited to 'llvm/lib/Transforms/Utils/NameAnonFunctions.cpp')
0 files changed, 0 insertions, 0 deletions