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| author | Javed Absar <javed.absar@arm.com> | 2017-03-27 20:46:37 +0000 |
|---|---|---|
| committer | Javed Absar <javed.absar@arm.com> | 2017-03-27 20:46:37 +0000 |
| commit | 3d594370933b515234c208a85a1c091d3e38d7f7 (patch) | |
| tree | 74e4b77190e8420c4d80ffe6096df575bc37525d /llvm/lib/Transforms/Utils/ModuleUtils.cpp | |
| parent | f1c2f2a668db86fc2143cfeeb3ff71579afabfbc (diff) | |
| download | llvm-3d594370933b515234c208a85a1c091d3e38d7f7.zip llvm-3d594370933b515234c208a85a1c091d3e38d7f7.tar.gz llvm-3d594370933b515234c208a85a1c091d3e38d7f7.tar.bz2 | |
Improve machine schedulers for in-order processors
This patch enables schedulers to specify instructions that
cannot be issued with any other instructions.
It also fixes BeginGroup/EndGroup.
Reviewed by: Andrew Trick
Differential Revision: https://reviews.llvm.org/D30744
llvm-svn: 298885
Diffstat (limited to 'llvm/lib/Transforms/Utils/ModuleUtils.cpp')
0 files changed, 0 insertions, 0 deletions