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| author | Charlie Turner <charlie.turner@arm.com> | 2015-11-09 12:45:11 +0000 |
|---|---|---|
| committer | Charlie Turner <charlie.turner@arm.com> | 2015-11-09 12:45:11 +0000 |
| commit | 7b7b06f73786ff8c6139a6337c565886ff4ba60e (patch) | |
| tree | 6fd387b07cc06efae2b0ebb80bd16ce1cf8edfbc /llvm/lib/Transforms/Utils/LoopVersioning.cpp | |
| parent | 4854d80c39270b9cd1e72b3e399045fbab768b6c (diff) | |
| download | llvm-7b7b06f73786ff8c6139a6337c565886ff4ba60e.zip llvm-7b7b06f73786ff8c6139a6337c565886ff4ba60e.tar.gz llvm-7b7b06f73786ff8c6139a6337c565886ff4ba60e.tar.bz2 | |
[AArch64] Handle extract_subvector(..., 0) in ISel.
Summary:
Lowering this pattern early to an `EXTRACT_SUBREG` was making it impossible to match larger patterns in tblgen that use `extract_subvector(..., 0)` as part of the their input pattern.
It seems like there will exist somewhere a better way of specifying this pattern over all relevant register value types, but I didn't manage to find it.
Reviewers: t.p.northover, jmolloy
Subscribers: aemerson, llvm-commits, rengolin
Differential Revision: http://reviews.llvm.org/D14207
llvm-svn: 252464
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopVersioning.cpp')
0 files changed, 0 insertions, 0 deletions